Infineon

Infineon IQE006NE2LM5SCATMA1

Infineon is presenting the new product of the portfolio extension for the innovative Source-Down technology: the OptiMOSTM 5 25 V PQFN 3.3x3.3 Source-Down DSC: IQE006NE2LM5SC. The revolutionary Source-Down technology introduces a flipped silicon die, which is positioned upside down inside of the components. This adjustment allows the source potential (instead of the drain potential) to be connected to the PCB over the thermal pad. Therefore, it offers several advantages, such as increased thermal capability, advanced power density or improved layout possibilities.Furthermore, the higher efficiency, the reduced active cooling requirements and the effective layout for thermal management are benefits at the system level. Thanks to the new benchmark RDS(on) and the innovative layout capacities enable the Source-Down concept to have a leading position in temperature management.Moreover, with the dual-side cooling package three times more power can be dissipated compared to the overmolded package. The Source-Down portfolio is addressing applications, such as drives, telecom, SMPS or server. The new technology can be found in two different footprints for now: Source-Down Standard-Gate and Source-Down Center-Gate (optimized for parallelization).
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Symbol Views

(not all views will be available for every part)

Normal: Standard and most popular representation of schematic symbol

ALT_1 (IEEE view): Symbol representation in a way that is more graphical in explaining what the purpose of each pin is. For connectors and most discretes (as we use these views) it is simply an alternate view for people to use depending on the situation. For instance connectors can be generally an input, an output or neither. Resistors can be vertical or horizontal.

ALT_2 (demorgan): Demorgan is a name for an equivalent Gate structure. so for instance an AND gate and an OR gate can be represented by its Demorgan equivalent of a NOR gate.

Sometimes a device is fractured into multiple symbols (often for high pin count parts). If that is the case, you can preview the different symbols that make up the device by selecting them in this drop down.

Footprint Views

(not all views will be available for every part)

Basic: Our standard footprint view showing, contact area, pin number, top, top assembly

Detailed: Additional info to help you evaluate the part and the footprint including: dimension, silkscreen, soldermask, and solderpaste

PinDetail: Highlights the pin to pad contact area dimensions

Displays min/typ/max pad sizes for footprint per IPC specification (not all sizes will be available for every part)

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Symbol Views

(not all views will be available for every part)

Normal: Standard and most popular representation of schematic symbol

ALT_1 (IEEE view): Symbol representation in a way that is more graphical in explaining what the purpose of each pin is. For connectors and most discretes (as we use these views) it is simply an alternate view for people to use depending on the situation. For instance connectors can be generally an input, an output or neither. Resistors can be vertical or horizontal.

ALT_2 (demorgan): Demorgan is a name for an equivalent Gate structure. so for instance an AND gate and an OR gate can be represented by its Demorgan equivalent of a NOR gate.

Sometimes a device is fractured into multiple symbols (often for high pin count parts). If that is the case, you can preview the different symbols that make up the device by selecting them in this drop down.

Footprint Views

(not all views will be available for every part)

Basic: Our standard footprint view showing, contact area, pin number, top, top assembly

Detailed: Additional info to help you evaluate the part and the footprint including: dimension, silkscreen, soldermask, and solderpaste

PinDetail: Highlights the pin to pad contact area dimensions

Displays min/typ/max pad sizes for footprint per IPC specification (not all sizes will be available for every part)